Metalens Manufacturing Scaling: Moving Flat Optics from Lab to Foundry

Transitioning metalens fabrication from small‑batch electron‑beam lithography to mass‑production semiconductor fabs forces a redesign of the optics, a switch in lithography technology, and new etching strategies.

The Nanostructure Bottleneck in Flat Optics

Metalenses swap the traditional curved glass element for a planar interface patterned with sub‑wavelength nanostructures. These features—meta‑atoms or nanopillars—control the phase, polarization and amplitude of transmitted light. Academic cleanrooms can prototype them reliably, yet scaling the designs to mass production stalls the technology. The obstacle is dimensional: visible and near‑infrared operation demands feature widths under 100 nm and pillar heights of a few hundred nanometers, which must be replicated with nanometer‑scale accuracy across wafer‑scale areas.

Serial Writing vs. Parallel Projection

In research labs electron‑beam lithography (EBL) remains the workhorse for fabricating metalenses. Its sub‑10 nm resolution lets scientists explore arbitrary pillar geometries and very tight pitches without the cost of photomasks. The technique, however, writes each nanopillar sequentially; a single beam must trace the entire pattern point by point. Consequently, printing a 10 mm‑diameter metalens can consume hours or even days, a timescale that precludes volume manufacturing. Commercially viable production therefore requires a shift to parallel optical projection lithography—specifically deep‑ultraviolet (DUV) steppers or scanners operating at 248 nm or 193 nm wavelengths.

These tools flood an entire reticle field in fractions of a second, making it possible to output tens of thousands of lenses per day on standard 200 mm or 300 mm silicon wafers.

Materials Compatibility and Etch Challenges

Academic research frequently uses materials that are incompatible with commercial semiconductor foundries. Materials like titanium dioxide (TiO2) or gallium nitride (GaN) offer excellent refractive indices and low loss in the visible spectrum, but foundries reject them due to potential cross-contamination of standard silicon processing lines. Consequently, engineers scaling metalenses must adapt designs to CMOS-compatible materials such as silicon nitride (SiN), amorphous silicon (a-Si), or silicon dioxide (SiO2). Beyond material choice, the etching process presents severe mechanical challenges. Nanopillars require high aspect ratios (often exceeding 10:1) to achieve a full 2-pi phase shift.

During reactive ion etching (RIE), maintaining vertical sidewall profiles without bowing, tapering, or physical collapse of the structures is highly difficult. Slight deviations in sidewall angles directly degrade the focusing efficiency of the final metalens.

Adapting Design Rules for Foundry Lithography

Transitioning from EBL to DUV photolithography requires a complete overhaul of the optical design rules. EBL allows sharp corners and high-contrast isolated features. In contrast, projection photolithography suffers from diffraction limits, causing corner rounding, line-end shortening, and critical dimension variation between dense and isolated regions. To combat these physical limitations, engineers must apply optical proximity correction (OPC) to the metalens design files. OPC modifies the shapes on the mask—adding serifs to corners or shifting edges—to ensure the printed structures on the wafer match the intended optical design.

Additionally, designers must restrict their layouts to comply with foundry Design Rule Checks (DRC), which enforce minimum feature sizes, grid alignments, and maximum aspect ratios.

Metrology and Yield Engineering for Metasurfaces

Standard semiconductor metrology tools are built to measure planar transistors and interconnect lines, not millions of dense, high-aspect-ratio optical nanopillars. Traditional critical dimension scanning electron microscopy (CD-SEM) only provides top-down 2D data, failing to capture sidewall angles or depth variations across the wafer. Cross-sectional transmission electron microscopy (TEM) is destructive and too slow for inline monitoring. Therefore, scaling efforts rely on non-destructive optical metrology techniques such as spectroscopic scatterometry (optical critical dimension, or OCD). OCD uses polarized light reflection and machine-learning models to reconstruct the 3D profile of the nanostructures in real time, allowing operators to adjust lithography and etch parameters before yield is compromised.

Integration and the Packaging Pathway

The final stage of metalens scaling is integration into standard optoelectronic packaging lines. Unlike silicon chips that are completely encapsulated, optical devices require clear optical paths. This demands specialized wafer-level packaging (WLP) where a glass cover wafer is bonded to the device wafer with precise spacer cavities, protecting the sensitive metasurface from dust and moisture without blocking light. Furthermore, because metalenses can be fabricated directly on flat glass or silicon substrates, they can be integrated directly onto CMOS image sensors at the wafer level.

This eliminates the active alignment step typically required for traditional multi-lens camera modules, significantly reducing assembly complexity and cost for consumer electronics, automotive sensors, and medical devices.