A 14-Bit 250-KS/s Calibration-Free SAR ADC for the Detection of Physiological Electrical Signals in Consumer Electronics

This research looks at designing high‑resolution, low‑power ADCs for reading physiological signals in consumer devices. Conventional high‑resolution SAR ADCs usually need complex calibration because of component mismatches. To avoid that, the paper presents a 14‑bit, 250‑kS/s hybrid resistor‑capacitor (R‑C) SAR ADC that requires no calibration. The architecture uses a special switching scheme to drive both the resistive DAC (RDAC) and the capacitive DAC (CDAC), keeping the common‑mode voltage stable. A redundant capacitor is added to the CDAC to reduce errors that arise when the signal does not fully settle during inter‑stage transitions. By combining resistors and capacitors, the design relaxes the strict matching requirements for each component while still delivering

good speed and accuracy. Post‑simulation results show an effective number of bits (ENOB) of 12.65 bits, differential nonlinearity (DNL) of –0.68 / +0.8 LSB, and integral nonlinearity (INL) of –1.4 / +0.84 LSB. For M.Tech students, this work provides a solid base for modeling mixed‑signal ICs, analyzing charge redistribution, and evaluating non‑linearity in MATLAB or Cadence Virtuoso.

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