Design low power energy efficient is a M.Tech project topic for Electronics & Communication Engineering. It gives students a clear starting point for research, implementation planning, and documentation.
Design low power energy efficient Project Details
| Abstract |
This research focuses on the design and detailed evaluation of an enhanced low-power, energy-saving, and high-resolution Sigma-Delta Analog-to-Digital Converter (ADC) tailored for biomedical Internet of Things (IoT) applications. Current technological developments require the integration of IoT devices that can handle large amounts of data with high accuracy while also ensuring low power consumption. This results in higher demands for the performance of data converters in wearable devices. The design and analysis of the Sigma-Delta ADC is done using the 180 nm SCL CMOS technology node in the Cadence Virtuoso environment. The main Sigma-Delta modulator incorporates a folded-cascode amplifier and a two-stage amplifier, optimized to provide a good trade-off between power
and accuracy. The folded-cascode amplifier provides a gain of 76 dB and a phase margin of 56 ° at the cost of a 250 µW power consumption. In contrast, the two-stage amplifier has a gain of 80.5 dB and a phase margin of 64 ° but with a much lower power consumption of 72 µW. To improve power efficiency further, the binary quantizer is replaced by a dynamic comparator circuit instead of the two-stage amplifier, which is anticipated to enhance the energy-efficient operation, supporting long battery life for biomedical IoT devices.
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| Reference Paper |
Design of low power energy efficient sigma-delta ADC for biomedical IoT applications |
| Domain |
Electronics Engineering |
| Sub-Domain |
Signal & Image Processing / Biomedical Signal Processing |
| PDF Download |
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