A Highly Integrated Multichip SiC MOSFET Power Module With Optimized Electrical and Thermal Performances

This research addresses the critical trade-offs between electrical, thermal, and electromagnetic interference (EMI) performances in multichip silicon carbide (SiC) MOSFET power modules. A highly integrated packaging architecture is evaluated, where two power switches are vertically stacked to minimize the physical power loop area. The design incorporates an internal decoupling circuit and an integrated liquid-cooling heatsink directly within the module structure to maximize heat dissipation. By co-optimizing the spatial arrangement and the electrical interconnects, the power loop parasitic inductance is minimized to approximately 2.02 nH, which significantly mitigates high-frequency voltage oscillations. Furthermore, the integrated decoupling path suppresses common-mode (CM) currents and reduces the transient drain-source voltage overshoot by up to 76.5%

during high-speed turn-off transitions. This project provides comprehensive academic guidance for modeling, simulating, and analyzing the electrothermal and electromagnetic behavior of the integrated module. Through finite element analysis (FEA) and transient circuit simulations, the methodology demonstrates how vertical stacking and integrated cooling resolve the historical conflicts between thermal dissipation and low-inductance electrical routing in wide-bandgap semiconductor packaging, offering a robust framework for high-power density converter designs.

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