signal-to-noise-and-distortion ratio noise-shaping sar adc is a M.Tech project topic for Electronics & Communication Engineering. It gives students a clear starting point for research, implementation planning, and documentation.
signal-to-noise-and-distortion ratio noise-shaping sar adc Project Details
| Abstract |
The work tackles the problem of building high‑resolution, low‑power analog‑to‑digital converters (ADCs) for biomedical sensor interfaces, where keeping thermal noise and offset voltage low is essential. It introduces a successive‑approximation‑register (SAR) ADC that combines a passive noise‑shaping (NS) method with a chopper‑stabilized comparator. The noise‑shaping part uses a cascade‑integrator feed‑forward (CIFF) structure that includes both infinite‑impulse‑response (IIR) and finite‑impulse‑response (FIR) filters. These filters reduce quantization noise and kT/C noise. To lower offset voltage and keep the circuit stable, a low‑power two‑stage chopper amplifier is placed inside the comparator loop. The design was fabricated in a 180 nm CMOS process. It reaches an effective number of bits (ENOB) of 10.6, a
signal‑to‑noise‑and‑distortion ratio (SNDR) of 68.4 dB, and a signal‑to‑noise ratio (SNR) of 59.33 dB. Powered from a 1.8 V supply, the ADC draws 650 µW and occupies 0.17 mm². The paper serves as a practical guide for M.Tech students who want to model, simulate, and evaluate passive noise‑shaping architectures and chopper‑stabilization techniques using MATLAB/Simulink or Cadence Virtuoso.
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| Reference Paper |
A Low-Power 68.4 dB Signal-to-Noise-and-Distortion Ratio Noise-Shaping SAR ADC for Biomedical Applications |
| Domain |
Electronics & Communication Engineering |
| Sub-Domain |
Signal & Image Processing / Biomedical Signal Processing / ECG/EEG Analysis |
| PDF Download |
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