A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

High‑speed, high‑resolution ADCs must balance thermal noise, power use, and chip area. This work looks at a compact 13‑bit, 200‑MS/s pipelined SAR ADC that includes a current‑biased ring amplifier and an active kT/C noise‑cancellation circuit. A current‑biasing scheme uses split capacitors to keep the ring amplifier stable despite process, voltage, and temperature (PVT) changes. Those same split capacitors let the kT/C noise‑cancellation method fit naturally into the pipelined SAR structure, so the input‑referred thermal noise can avoid the usual input‑sampling kT/C noise limit. As a result, the input sampling capacitance can be reduced to a single‑ended 128 fF. The design occupies only 0.004 mm² of active core area in a

28‑nm CMOS process. It delivers a signal‑to‑noise‑and‑distortion ratio (SNDR) of 67 dB while drawing 1.3 mW at a 200‑MS/s sampling rate. The project also offers practical guidance and research direction for modeling, simulating, and evaluating the noise‑cancellation performance and PVT stability of this pipelined SAR ADC architecture.

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