A Bi-CMOS electronic photonic integrated circuit quantum light detector.

Putting electronic and photonic parts together on a single silicon chip is a key step for quantum communication and ultra‑fast optical processing. This work looks at how to design, model, and test a Bi‑CMOS electronic‑photonic integrated circuit (EPIC) that is tuned for detecting quantum‑level light. The chip combines silicon‑germanium (SiGe) heterojunction bipolar transistors (HBTs) with waveguide‑integrated photodetectors. By doing this, the design cuts down parasitic capacitance and improves the signal‑to‑noise ratio when the optical power is extremely low. The approach uses multi‑domain simulations of the optoelectronic interface, with special attention to the transimpedance amplifier (TIA) stage and how the photodiode is integrated. The study evaluates several key performance numbers: –

Dark current – Responsivity – Bandwidth – Equivalent noise charge To support the implementation, the project creates equivalent circuit models, runs optical propagation simulations, and performs parametric optimization of the Bi‑CMOS front‑end. This framework gives clear guidance for balancing speed, noise performance, and integration density in the next generation of quantum photonic receivers.

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