A Pulse-Skipping Soft-Start Circuit for DC-DC Converters

During the startup phase of DC-DC converters, the rapid charging of off-chip capacitors typically induces severe inrush currents and voltage overshoots, which can degrade system reliability and damage sensitive load circuitry. Traditional mitigation techniques, such as reducing the charging current or increasing the soft-start capacitance, often compromise system stability or escalate manufacturing costs. To address these limitations, this project focuses on the design and simulation of an integrated pulse-skipping soft-start circuit. The proposed methodology utilizes a controlled current source to charge the soft-start capacitor intermittently via a pulse-skipping mechanism. This approach ensures a gradual, monotonic rise of the error amplifier's reference signal during power-up, thereby extending the soft-start duration and

effectively suppressing inrush currents. The architecture is modeled and evaluated using standard 0.18 μm BCD process parameters. Simulation and analysis support the verification of a 2.5 ms soft-start period, demonstrating smooth output voltage transitions and minimal silicon area overhead. This research provides a structured framework for implementing cost-effective, highly stable startup controllers suitable for portable medical and consumer electronic applications.

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